1. Field of the Invention
The invention relates to a time of arrival encoder, and more particularly relates to a high resolution event occurrence time counter useful in applications where high precision time interval measurements are necessary.
2. Objects and Summary of the Invention
It is an object of the present invention to provide an event occurrence time counter which provides a high resolution time interval measurement.
It is another object of the present invention to provide an event occurrence time counter adapted for use at clock frequencies in the Gigahertz range.
It is yet another object of the present invention to provide a event occurrence time counter circuit which is adapted to measure the interval of time following the occurrence of an event to within an accuracy of one-half the clock period.
It is yet a further object of the present invention to provide an event occurrence time counter which provides time interval measurement data with minimal ambiguity.
It is yet a further object of the present invention to provide a positive means to assure that a particular type of counter, i.e., a Johnson type counter, will operate properly without the necessity for an external reset which, if improperly applied, can cause improper operation of the counter. Said means assures proper sequence after as many clocks as there are stages in the counter and assures operation for all cycles thereafter and a recovery in the event of a clock anomaly.
It is yet a further object of the present invention to provide an implementation which requires no alignments or adjustments either initially or upon replacement of any of its constituent elements and remains impervious to physical and temperature effects, providing implementation constraints are satisfied.
In accordance with one form of the present invention, a high resolution event occurrence time counter includes a free running counter which is responsive to a clock signal, such as a periodic logic signal having a frequency on the order of a Gigahertz or more. The counter provides a count data of binary form, which data varies in response to the clock signal.
The event occurrence time counter further includes a first register which stores the count data of the free running counter in response to the clock signal or, more specifically, its inverse. The count data is stored in the first register at least one-half period after the count data has changed in the counter in response to the leading edge of the clock signal. The first register provides first register data which represents the count data stored in the first register.
A second register stores the first register data, and provides first time of arrival data representative of the first register data.
A third register stores the count data of the free running counter, and provides second time of arrival data representative of the count data that is stored in the third register.
The event occurrence time counter further includes a clock edge encoder. The clock edge encoder determines whether an event has occurred during either the first half period of the clock signal or the second half period. The clock edge encoder provides a first sync signal when the event occurred during the first half period, and a second sync signal when the event occurred during the second half period.
The second register stores the first register data in response to the first sync signal, and the third register stores the count data of the counter in response to the second sync signal.
Depending on when the event occurred, that is, either in the first half period of the clock signal or in the second half period, at least the first time of arrival data or at least the second time of arrival data is provided as output data of the event occurrence time counter.
Basically, the event occurrence time counter works in the following manner. The counter and first register are clocked on opposite edges of the input clock signal. Depending upon during which half period of the clock signal an event occurs, the event occurrence time counter will provide output data which is the more stable of the count data of the counter or the first register data of the first register.
The counter is updated (i.e., clocked) at the mid-point of each period of the clock signal, that is, directly after the first half period. If the event occurs within the first half period of the clock signal, the counter may not have fully stabilized and the count data may be ambiguous.
However, the first register has the count data of a previous clock period stored in it, which data is assured of being stable because the count data is clocked into the first register at the end of each clock period (i.e., after the second half period). In other words, the count data has had sufficient time to settle out so that the data is not in a transition phase when it is clocked into the first register.
Accordingly, if the event occurs in the first half period of the clock signal, the event occurrence time counter will output the more stable data, which is the count data from the previous period or cycle stored in the first register. This first register data is stored in the second register upon generation of a first sync signal and is chosen as the time of arrival output data by the event occurrence time counter.
If the event occurs in the second half period of the clock signal, the more stable and accurate of the first register data and the count data is the count data. This is because the first register data may be changing, as the count data is being loaded into the first register at the end of the second half cycle of clock signal and the first register data may be in a transition phase. The counter, on the other hand, has stabilized by the end of the second half period, and its count data is unambiguous. The stable count data is stored in the third register upon generation of a second sync signal (indicating that the event occurred in the second half clock period) and is chosen as the time of arrival output data by the event occurrence time counter.
The clock edge encoder will determine which data the event occurrence time counter should output, that is, either the first time of arrival data of the second register representing the first register data (which is, in effect, the count data of the previous cycle), or the second time of arrival data of the third register representing the count data for the present cycle. Because the clock edge encoder determines in which half cycle the event occurred, and chooses the output data of the event occurrence time counter accordingly, an indication of the half cycle in which the event occurred is known and is provided as the least significant bit of the output data.